1. Field of the Invention
This invention relates generally to a non-volatile integrated circuit memory. More particularly this invention relates to electrically erasable programmable read only memory (EEPROM) and flash electrically erasable programmable read only memory (flash memory).
2. Description of Related Art
The structure and application of the floating gate nonvolatile memories is well known in the art. The floating gate nonvolatile memory has three classifications the Electrically Programmable Read Only Memory (EPROM), the Electrically Erasable Programmable Read Only Memory (EEPROM), and the flash Electrically Erasable Programmable Read Only Memory. The EPROM is programmed by electrically forcing charge to the floating gate. Ultra-violet light is employed to eliminate the electrical charges of the programming from the floating gate of the EPROM. The EEPROM and the flash memory are structurally similar at the individual cell, but have different organizations. The EEPROM and the flash memory maybe have the charge transferred to the floating gate for programming by either a channel hot injection of the charge or by Fowler-Nordheim Tunneling through a tunneling oxide. The erasure of the EEPROM and Flash memory is generally by a Fowler-Nordheim Tunneling through the tunneling oxide.
A primary application of a nonvolatile memory is for permanent memory in a microprocessor or microcontroller system. Historically, the permanent program memory for the microprocessor was formed of classic mask programmable read only memory (ROM), and later as EPROM. Modifications to the program memory required physically changing the memory. As the need to update the program of the microprocessor became more important, byte-alterable EEPROM were developed to provide in-system rewriteability of the memory. Further as the applications for microprocessors and microcontrollers are becoming more pervasive, the need for storage that is permanent and will not fail or disappear when power is removed is required. In most applications, the program is not modified often. However, the data is changed relatively frequently. The program memory can be classified as configuration, traceablity, boot program, or main program. The data includes information from any external input to the system, e.g., application, instrument, recorder, or sensor data that is required for historical purposes or to maintain continuity of operation after power down or power loss. Data memory is typically frequently altered over the lifetime of the application.
The program memory is generally implemented in Flash memory. The Flash memory has memory size per erase that is usually large and is in the units of sector that ranges from 8 KB (64K-bit) to 64 KB (6512K-bit). Alternately, the data memory is implemented as EEPROM. The EEPROM used for a data memory must have segments that may be erased as small as single byte (8 bits), to a size of a single page (128-byte), and even to erasure of the whole chip.
The ability of the EEPROM and the Flash memory to be reprogrammed requires the device be able to be altered in system, with minimal hardware or software difficulty. The number of times the device must be altered determines the endurance requirement of the device. Nonvolatility requires the device to retain data without power applied for the lifetime of the application. The lifetime of the application determines the data retention requirement of the device. Both of the reliability requirements of endurance and data retention have associated failure rates, which must be minimized. Since the flash memory is employed as the program memory, it has the least amount of reprogramming and therefore, must have the longest data retention and requires the lowest endurance (approximately 100,000 program/erase cycles). Conversely, the EEPROM, employed as data memory, must be able to be modified repeatedly and therefore must have higher endurance (more than 1 million program erase cycles).
In order to achieve the one million program/erase cycles and have the single-byte erase segment, the traditional EEPROM employs a very large cell size (approximately 100 times the minimum feature size of the technology). Alternately, the flash memory can have a cell size that is significantly smaller (approximately 10 times the minimum feature size of the technology).
In applications requiring high data rate change such as the data memory, as described, the nonvolatile memory requires a faster date change (program/erase) cycle. Thus the EEPROM requires a write or program speed of 1 ms. Alternately, the flash memory can tolerate a write speed that is on the order of 100 ms.
FIGS. 1a-d illustrates a floating gate memory cell of the prior art. The flash memory cell 10 is formed within a p-type substrate 2. An n+ drain region 6 and an n+ source region 4 are formed within the p-type substrate 2.
A relatively thin gate dielectric or tunneling oxide 8 is deposited on the 15 surface of the p-type substrate 2. A poly-crystalline silicon floating gate 12 is formed on the surface of the tunneling oxide 8 above the channel region 5 between the drain region 6 and source region 4. An interpoly dielectric layer 14 is placed on the floating gate 12 to separate the floating gate 8 from a second layer of poly-crystalline silicon that forms a control gate 16.
In most applications of an EEPROM or flash memory, the p-type substrate 2 is connected to a substrate biasing voltage, which in most instances is the ground reference potential (0V). The source region 4 is connected to a source voltage generator through the source line terminal 22. The control gate 16 is connected through the word line terminal 20 to the control gate voltage generator. And the drain region 6 is connected through the contact 24 to the bit line and thus a bit line voltage generator.
The memory cell 10 is separated from adjacent memory cells or circuits of an integrated circuit on a substrate by the shallow trench isolation 26. The shallow trench isolation 26 provides a level isolation from disturbing signals from any operations of the adjacent cells.
As is well known, the coupling ratio of the control gate 16 and floating gate 12 are critical in determining the magnitude of voltage applied across the tunneling oxide 8 to cause the flow of charge to or from the floating gate 12. Thus it is desirable to maintain a relatively large coupling ratio for the floating gate 12. To accomplish this, the floating gate is extended over the shallow trench isolation 26 to form what is commonly termed “wings” 28. The “wings” 28 allow the voltages applied across the control gate 16 to be relatively lower and still allow the charges to flow to and from the floating gate 12. However, the “wings” prevent the design of the memory cell 10 from achieving a minimum size.
According to conventional operation, the memory cell 10 is programmed by applying a relatively high voltage (on the order of 10V) to the control gate 16 through the word line 20. The drain voltage generator VD is set to a moderately high voltage (on the order of 5V), while the source voltage generator VS is set to the ground reference potential (0V). With these voltages hot electrons will be produced in the channel 5 near the drain region 6. These hot electrons will have sufficient energy to be accelerated across the tunneling oxide 8 and trapped on the floating gate 12. The trapped hot electrons will cause the threshold voltage of the field effect transistor (FET) that is formed by the memory cell 10 to be increased by three to five volts. This change in threshold voltage by the trapped hot electrons causes the cell to be programmed from the unprogrammed state of a logical one (1) to a logical zero (0).
Conventionally, the memory cell is erased by setting the word line 20 to a relatively large negative voltage on the order of −18V. The bit line 18 and the source line 22 may be disconnected to allow the drain 6 and the source 4 to float. Alternately, the bit line 18 and the source line 22 are connected such that the drain 6 and the source 4 are connected to the ground reference voltage. Under these conditions there is a large electric field developed across the tunneling oxide 8 in the channel region 5. This field causes the electrons trapped in the floating gate 12 to flow to channel region 5, drain region 6 and source region 4. The electrons are then extracted from the floating gate 12 by the Fowler-Nordheim tunneling. This change in threshold voltage by the removal of the trapped hot electrons causes the cell to be erased (unprogrammed) state
If the memory cell is to be written with a logical one (1), the cell is not programmed and no or little negative charges are placed on the floating gate 12. Thus, if the cell is erased, the relatively large negative voltage applied to the control gate 16 through the word line 20 causes the memory cell 10 to become over-erased. Positive charges actually are stored on the floating gate 12. This phenomenon causes the Field Effect Transistor (FET) of the memory cell 10 to become depletion-mode transistor and the drain 6 and the source 4 to become essentially shorted. When this occurs, the memory cell 10 causes false reading of data from a selected memory cell on a shared bit line of an array having an over-erased memory cell. To overcome this problem, a select gating transistor STx 30 is placed between the memory cell 10 and the source line 22, as shown in FIG. 2a-c. This prevents any excess current through the memory cell 10 when the select gating transistor STx 30 remains in the off-state.
Refer now FIGS. 2a-2c for further discussion of the two transistor memory cell of the prior art. The memory cell 10 is formed within a p-type well 36 that is formed in an n-type well 34 on a p-type substrate 2. An n+ drain region 4 and an n+ source region 6 are formed within the p-type well 36.
A relatively thin tunneling oxide 8 is deposited on the surface of the p-type substrate 2. A poly-crystalline silicon floating gate 12 is formed on the surface of the tunneling oxide 8 above the channel region 5 between the drain region 6 and source region 4. An interpoly dielectric layer 14 is placed on the floating gate 12 to separate the floating gate 12 from a second layer of poly-crystalline silicon that forms a control gate 16.
The source 4 fundamentally is the drain of the select gating transistor 30. The source 38 of the select gating transistor 30 is formed simultaneously with the drain 6 and the source 4 of the memory cell 10. The gate 40 of the select gating transistor 30 is placed over the gate oxide 39 between the source 4 of the memory cell 10 and the source 38 of the select transistor 30.
When the tunneling oxide 8 is formed, a gate oxide 39 is formed in the channel region between the source 4 of the memory cell 10 and the source 38 of the select transistor 30. The gate 40 is connected to the select control line SG, which conducts a select signal to the select gating transistor 30 to control the impact of the over-erasure of the memory cell.
In most applications, of an EEPROM or flash memory having the two transistor configuration, the p-type well 36 is connected to a substrate biasing voltage, which in most instances is the ground reference potential (0V). The source region 38 of the select gating transistor 30 is connected to a source voltage generator through the source line terminal 22. The control gate 16 is connected through the word line terminal 20 to the control gate voltage generator. The select gating line 32 is connected to a select signal generator to provide the select signal to the gate 40 of the select gating transistor 30. And the drain region 4 is connected through the contact 24 to the bit line 18 to a bit line voltage generator.
The memory cell 10 and select gating transistor are separated from adjacent memory cells or circuits of an integrated circuit on a substrate by the shallow trench isolation 26. The shallow trench isolation 26 provides a level isolation from disturbing signals from any operations of the adjacent cells.
As is well known and described above, the floating gate is extended over the shallow trench isolation 26 to form the “wings” 28. The “wings” 28 allow the voltages applied across the control gate 16 to be relatively lower and still allow the charges to flow to and from the floating gate 12. However, the “wings” prevent the design of the memory cell 10 from achieving a minimum size.
The memory cell 10 is programmed by setting the drain 6 of the memory cell 10 must be set to a voltage or more than +15.0V. The control gate 16 is set at the ground reference voltage level and the source 4 is made to float by disconnecting the source line to avoid a current leakage. The +15.0V voltage present at the drain 6 and the channel 5 is coupled from bit line 18. The gate 40 through the select gate 32 is set to a ground reference voltage. This causes the high voltage of the drain 6 and the channel 5 causes a Fowler-Nordheim Tunneling of the charges from the floating gate 12 to drain 6.
Conventionally, the memory cell is erased by setting the word line and thus the control gate 16 are biased at around +15.0V-+17.0V. The drain 6 through the bit line 18 and source 4 through the select gating transistor 30 and the source line 22 are both held at the ground reference voltage level. The gate 40 of the select gating transistor 30 is placed at a voltage of from +3.0V-+5V and the bit line 18 is placed at the ground reference voltage to ensure that the drain 4 is set to the ground reference voltage.
Other configurations of the memory cells are known in the art that increase the coupling coefficient through increasing the area at which the control gate and the floating gate are tightly coupled. Other configurations effectively merge the select gating transistor and the memory cell to help improve the cell size. Still other configurations provide more gating transistors that isolate the memory cell from the bit line as well as the source line to prevent disturbances from operations on cells connected to the bit lines and the source lines. Examples of these and other configurations are described hereinafter.
U.S. Pat. No. 6,370,081 (Sakui, et al.) describes a nonvolatile memory cell having a memory cell and two select transistors sandwiching the memory cell. One block of memory nonvolatile memory cells has one control gate line. The nonvolatile memory cells are connected to one control gate line form one page. A sense amplifier having a latch function is connected to a bit line. In a data change operation, data of memory cells of one page are read to the sense amplifiers. After the data is sensed and stored in the sense amplifiers a page erase is performed. The data from the sense amplifiers are programmed in the memory cells of one page. Data in the sense amplifiers maybe changed in the sense amplifiers prior to the reprogramming to allow byte or page data programming.
U.S. Pat. No. 6,400,604 (Noda) teaches a nonvolatile semiconductor memory device having a data reprogram mode. The memory has a memory cell array, a page buffer for storing one page data to be programmed to memory cells, which are selected in accordance with a page address signal. The memory further has an internal column address generating circuit for generating column addresses of the one page with inputting the page address signal in order to transfer the one data stored in the page buffer to the memory cells, a column decoder receiving the column addresses from the internal column address generating circuit, and a control circuit having a data reprogram mode. The data reprogram mode erases one page data stored in the memory cells which are selected in accordance with the page address signal and programs the one page data stored in the page buffer to the memory cells which are selected.
U.S. Pat. 6,307,781 (Shum) provides a two transistor cell NOR architecture flash memory. The floating gate transistor is placed between the selection transistor and an associated bit line. The flash memory is deposited within a triple well and operates according to a Fowler-Nordheim tunnel mechanism. Programming of memory cells involves tunneling of carriers through gate oxide from a channel region to a floating gate rather than tunneling from a drain or source region to the floating gate.
U.S. Pat. No. 6,212,102 (Georgakos, et al.) illustrates an EEPROM with two-transistor memory cells with source-side selection. The voltage required to program a memory cell is delivered via a source line.
U.S. Pat. No. 6,266,274 (Pockrandt, et al.) regards a non-volatile two-transistor memory cell which has an N-channel selection transistor and an N-channel memory transistor. The drive circuitry for the cell includes a P-channel transfer transistor. A transfer channel is connected to a row line leading to the memory cell.
U.S. Pat. No. 6,174,759 (Verhaar, et al.) teaches an EEPROM cell that is provided with such a high-voltage transistor as a selection transistor similar to that described in FIGS. 2a-c. Apart from the n-well implantation, high-voltage transistors of the p-channel are largely manufactured by means of the same process steps as the p-channel transistors in the logic, so that the number of process steps remains limited.
U.S. Pat. No. 6,326,661 (Dormans, et al.) describes a floating gate memory cell having a large capacitive coupling between the control gate and the floating gate. The control gate is capacitively coupled to the substantially flat surface portion of the floating gate and to at least the side-wall portions of the floating gate facing the source and the drain, and ends above the substantially flat surface portion of the select gate. This provides a semiconductor device having a large capacitive coupling between the control gate and the floating gate of the memory cell thus increasing the coupling ratio.
U.S. Pat. No. 5,748,538 (Lee, et al.), assigned to the same assignee as the present invention, describes an OR-plane memory cell array for flash memory with bit-based write capability. The memory cell array of a flash electrically erasable programmable read only memory (EEPROM) includes nonvolatile memory cells arranged in rows and columns. The sources of nonvolatile memory cells in the same memory block are connected to a main source line through a control gate. Similarly, the drains of the nonvolatile memory cells of the same memory block are connected to a main bit line. The separate source and drains in the column direction are designed for a bit-based write capability. Writing, such as erasing or programming, of a selected nonvolatile memory cell uses the Fowler-Nordheim tunneling method and can be accomplished due to the programming or erase inhibit voltage that is applied to non-selected nonvolatile memory cells.